1. Field of the Invention
The present invention relates to testing of integrated circuits using sequential scan based techniques, and more specifically to a method and apparatus for testing interface between modules designed to operate at different clock frequencies.
2. Related Art
Sequential scan techniques are often used to test integrated circuits. According to a typical sequential scan technique, integrated circuits are designed to operate in functional mode or test mode. In functional mode, elements in the integrated circuit are connected according to a desired design and to provide a desired utility for which the integrated circuit is primarily designed.
In test mode, the integrated circuit is designed to connect various memory elements (contained in the integrated circuit) such as flip-flops in a sequence referred to as a “scan chain” (i.e., the output of one element is connected as an input to the next element). The first element in the scan chain is generally designed to receive the input bits and the last element of the scan chain is designed to scan out the results of evaluation, as described below.
In a typical scan test scenario, a number of bits in a particular pattern of zeros and ones (scan vector) are sequentially (one bit at every clock cycle) loaded (scanned in) into a scan chain through the first element. The number of bits contained in the scan vector generally equals the number of memory elements in a corresponding scan chain.
Once a scan chain is loaded with a scan vector, the elements (generally the combinatorial logic) in the integrated circuit are evaluated by connecting the elements in the integrated circuit according to the connections defined for functional mode of operation. The integrated circuit is operated generally for one clock cycle similar to in the functional mode and the corresponding duration may be termed as the evaluation phase. Based on the scanned in bits, the flip-flops latches the results of the functional mode operation of one clock pulse.
The connection is then reverted back to the test mode, and the bits latched are sequentially scanned out (one bit at every clock cycle) through the last element in the scan chain. The received scan out is compared with an expected scan out corresponding to the scan vector to determine the various faults within the integrated circuit.
There is a general need to use such scan techniques even in situations when an integrated circuit (device or system) contains multiple modules. Modules generally refer to distinct units, typically provided for a specific purpose. For example, a module may operate as a random access memory, and another module may be implemented to process analog signals according to desired digital signal processing (DSP) techniques.
It is desirable that to test the inter-module operation, generally when one module is designed to provide a signal to another module. The modules are generally said to be connected by interface logic, which can be a combinatorial circuit (performing a logical operation), a straight metal path connecting the modules, etc.
Testing of inter-module operation is known to present challenges, particularly when the modules are designed to operate at different clock frequencies in functional mode. In one prior approach, each module is tested separately at a corresponding clock frequency only. Thus, each module is tested individually, but inter-module operation may not be at least adequately tested.
In another prior approach, the two modules are tested together, but using a common clock frequency. As a result, the accuracy of logic of inter-module operation may be tested. However, such an approach may not test the inter-module operation for any faults related merely to timing. For example, the prior approach may not test for transition faults. A transition fault is generally said to be present if a node fails to transition from one logical value to another logical value in a desired time interval (determined by the frequency of operation of the clock).
Hence what is generally needed is a method and apparatus for testing interface between modules designed to operate at different clock frequencies.
In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.